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ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor features ar0835hs_ds rev. d pub. 5/15 en 1 ?semiconductor components industries, llc 2015, 1/3.2-inch 8 mp cmos digital image sensor ar0835hs datasheet, rev. d for the latest datasheet, please visit www.onsemi.com features ? high speed sensor supporting 8 mp (4:3) and 6 mp (16:9) up to 60 fps ? 1.4 ? pixel with on semiconductor a-pixhs? technology providing best-in-class low-light performance ? optional on-chip high-quality bayer scaler to resize image to desired size ? data output serial interface: four-lane high-speed serial pixel interface (hispi) or mobile industry processor interface (mipi) ? bit-depth compression available for serial interface: 10-to-8 and 10-6 bit compression to enable lower bandwidth receivers for full frame rate applications ? on-chip temperature sensor ? on-die phase-locked loop (pll) oscillator ? 5.6 kbits one-time prog rammable memory (otpm) for storing module information and calibration data ?on-chip 8-bit vcm driver ? 3d synchronization controls to enable stereo video capture ? interlaced multi-exposure readout enabling high dynamic range (hdr) stil l and video applications ? programmable controls: gain, horizontal and vertical blanking, auto black le vel offset correction, frame size/rate, exposure, left?right and top?bottom image reversal, window size, and panning ? support for external mechanical shutter ? support for external led or xenon flash applications ?sports cameras ? digital still cameras ? digital video cameras table 1: key performance parameters parameter typical value array format 8 mp: 3264 x 2448, 6 mp: 3264 x 1836 primary modes 4:3 - 8 mp 46 fps max (hispi) and 42 fps max (mipi) 16:9 - 6 mp at 60 fps max 1080p 60 fps / 720p 120 fps max pixel size 1.4 ? m back side illuminated (bsi) optical format 1/3.2" die size 6.86 mm x 6.44 mm (area: 44.17 mm 2 ) input clock frequency 6 - 27 mhz interface hispi mode: 4 lanes at 1 gbps max. mipi mode: csi-2 (2,3,4 lanes) at 896 mbps max. subsampling modes x - bin2, sum2 skip: 2x, 4x y - sum2, skip: 2x, 4x, 8x output data depth 10-bit raw, 10-to-8 bit a-law, 8/6-bit dpcm analog gain 1x, 2x, 3x, 4x, 6x, 8x high quality bayer scalar adjustable scaling up to 1/6x scaling temperature sensor 10-bit, single instance on chip, controlled by two-wire serial i/f vcm af driver 8-bit resolution with slew rate control 3-d support frame rate and exposure synchronization supply voltage analog 2.5 - 3.1 v (2.8 v nominal) digital 1.14 - 1.3 v (1.2 v nominal) pixel 2.5 - 3.1 v (2.8 v nominal) i/o 1.7 - 1.9 v (1.8 v nominal) or 2.5 - 3.1 v (2.8 v nominal) hispi/ mipi 1.14 - 1.3 v (1.2 v nominal) otpm program voltage 6.5v power consumption typical 420 mw at 25c for 8m/46 fps and 6m/60 fps responsivity 0.6 v/lux-sec
ar0835hs_ds rev. d pub. 5/15 en 2 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor ordering information notes: 1. 1 gbps/lane hispi and 896 mb ps/lane mipi data transfer rate 2. values measured at t=25 c and nominal voltages. ordering information snr max 36 db dynamic range 64 db operating temperature range (at junction) -t j -30 c to +70 c table 2: modes of operation and power consumption mode active readout window (col x row) sensor output resolution (col x row) mode fps typical power consumption [mw] 2 full resolution 4:3 8mp 3264 x 2448 3264x2448 full mode 46/42 420 8mp 3264 x 2448 3264x2448 full mode 30 370 full resolution 16:9 6mp 3264x1836 3264x1836 full mode 60 420 6mp 3264x1836 3264x1836 full mode 30 370 4:3 video mode vga 3264 x 2448 640 x 480 skip4 180 370 qvga 3264 x 2448 320x240 skip4 240 370 16:9 video mode 1080p 3264 x 1836 1920 x 1080 scaling 30 360 1080p 3264x1836 1920x1080 scaling 60 420 720p 3264 x 1836 1280 x 720 bin2-sum2 120 390 720p 3264 x 1836 1280 x 720 scaling 60 420 720p 3264 x 1836 1280 x 720 bin2 + scaling 60 250 table 3: available part numbers part number product description orderable product attribute description ar0835hs3c12suaa0-dp 8 mp 1/3" cis dry pack with protective film AR0835HS3C12SUAA0-DR 8 mp 1/3" cis dry pack without protective film table 1: key performance parameters (continued) parameter typical value
ar0835hs_ds rev. d pub. 5/15 en 3 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 typical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 sensor initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 integration time for interlaced hdr readou t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 internal vcm driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 hispi specification reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 mipi specification reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 package diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
ar0835hs_ds rev. d pub. 5/15 en 4 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor list of figures list of figures figure 1: top level block diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: pixel color pattern detail (top ri ght corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical application ci rcuit?hispi connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5: recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: recommended power-down sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 7: hard standby and hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 8: soft standby and soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 9: single read from random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 10: single read fr om current location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 11: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 12: sequential read, start from curre nt location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 13: single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 14: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 15: clocking configuration (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 16: hdr integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 17: bayer resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 18: results of resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 19: illustration of resampling oper ation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 20: effect of horizontal_mirror on readout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 21: effect of vertic al_flip on readout order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 22: effect of x_odd_inc = 3 on readout sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 23: effect of x_odd_inc = 7 on readout sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 24: pixel readout (no subsampling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 25: skip2 pixel readout (x_odd_inc = 3, y_odd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 26: skip4 pixel readout (x_odd_inc = 7, y_odd_inc = 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 27: bin2 pixel readout (x_odd_inc = 3, y_odd_inc = 1, x_bin = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 28: bin2pixel readout (x_odd_inc = 3, y_odd_inc = 3, x_bi n = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 29: pixel binning and summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 30: xenon flash enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 31: led flash enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 32: overview of global reset sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 33: entering and leaving a global re set sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 34: controlling the reset and integration phases of the gl obal reset sequence . . . . . . . . . . . . . . . . . . . .47 figure 35: control of the electromechanica l shutter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 36: controlling the shutter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 37: using flash with global reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 38: extending flash duration in global reset (reference readout start) . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 39: global reset bulb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 40: entering soft standby during a global reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 41: slave mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 42: vcm driver typical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 43: quantum efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 44: chief ray angle (cra) vs. image height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 45: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 46: fall slew rates (cap load = 25pf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 47: rise slew rates (cap load = 25pf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 48: hispi transmitter and receiver interface block diagram (his pi mode only) . . . . . . . . . . . . . . . . . . .61 figure 49: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 50: block diagram of dll timing ad justment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 51: delaying the clock_lane with re spect to data_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 52: delaying data_lane with respect to the clock_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 53: clcc package diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 54: clcc package pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
ar0835hs_ds rev. d pub. 5/15 en 5 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: modes of operation and power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 4: pad descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 5: independent power and ground domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 6: inrush consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 7: power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 8: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 9: address space regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 10: data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 11: row address sequencing during subs ampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 12: column address sequencing during binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 13: row address sequencing during binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 14: available skip, bin, and sum modes in the ar0835hs sens or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 15: minimum frame time and blanking numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 16: recommended analog gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 17: vcm driver typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 18: two-wire serial register interface electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 19: two-wire serial interfac e timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 20: electrical characterist ics (extclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 21: slvs electrical timing specificat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 22: slvs electrical dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 23: dc electrical characteristics (con trol interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 24: dc electrical definitions and char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 25: typical operating current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 26: absolute max voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
ar0835hs_ds rev. d pub. 5/15 en 6 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor general description general description the on semiconductor ar0835hs is a 1/3.2- inch bsi (back side illuminated) cmos active-pixel digital image sensor with a pixel array of 3264h x 2448v (3280h x 2464v including border pixels). it incorporates so phisticated on-chip camera functions such as mirroring, column and row skip modes, and context switching for zero shutter lag snap- shot mode. it is programmable through a simp le two-wire serial interface and has very low power consumption. the ar0835hs digital image sensor featur es on semiconductor's breakthrough low- noise 1.4 ? m pixel cmos imaging technology that achieves near- ccd image quality (based on signal-to-noise rati o and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. functional overview in order to meet higher frame rates in ar0835hs sensor, the architecture has been re- designed. the analog core has a column parallel architecture with 4 data paths. digital block has been re-architected to have 4 data paths. figure 1 shows the block diagram of the ar0835hs. figure 1: top level block diagram the core of the sensor is an 8mp active-p ixel array. the timing and control circuitry sequences through the rows of the array, rese tting and then reading each row in turn. in the time interval between resetting a row and re ading that row, the pixels in the row inte- grate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing ga in), and then through an adc. the output from the adc is a 10-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which pr ovides further data path corrections and applies digital gain). hispi/mipi serial data output [3:0] v aa , v aa _pix v dd _io, dv dd _1v8, dv dd _1v2 pixel array row driver 10-bit temperature sensor gain control gain adc vcm fifo & optional compression hispi data calibration imaging sensor core digital processing -wire digital gain scaler test pattern generator xshutdown image output gpi[3:2] external clock pll gpio[1:0] vcm control dv dd _1v2_phy two wire serial interface s data s clk register control ar0835hs timing control
ar0835hs_ds rev. d pub. 5/15 en 7 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor functional overview the pixel array contains optically active and light-shielded (?dark?) pixels. the dark pixels are used to provide data for on-chip offset-correction algorithms (?black level? control). the sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers can be accessed through a two-wire serial interface. the output from the sensor is a bayer pattern ; alternate rows are a sequence of either green and red pixels or blue and green pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. a flash output signal is provided to allow an external xenon or led light source to synchronize with the sensor exposure time. additional i/o signals support the provision of an external mechanical shutter. pixel array the sensor core uses a bayer color pattern, as shown in figure 2. the even-numbered rows contain green and red pixels; odd-numbered rows contain blue and green pixels. even-numbered columns contain red and green pixels; odd-numbered columns contain blue and green pixels. figure 2: pixel color pattern detail (top right corner) note: by default the mirror bit is set, so th e read-out direction is from right to left. g2 r gb r gb g2 r gb r gb b gr b gr b g2 r gb r gb b gr b gr b g2 r g2 r g2 black pixels column readout direction . . . ... row readout direction first pixel (col. 0, row 60)
ar0835hs_ds rev. d pub. 5/15 en 8 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor typical connections typical connections the chip supports hispi/mipi output protoc ol. hispi and mipi are configured to work in 4-lane mode. there are no parallel data output ports. figure 3: typical application circuithispi connection for connectivity above: 1. all power supplies should be adequately decoupled; recommended cap values are: ? 2.8v: 1.0 ? f, 0 . 1 ? f, and then 0.01 ? f ? 1.2v: 10 ? f, 1 ? f, and then 0.1 ? f ? 1.8v: 1 ? f and 0.1 ? f 2. resistor value 1.5k is recommended, but ma y be greater for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. v aa and v aa _pix can be tied together. however, for noise immunity it is recom- mended to have them separate (i.e . two sets of 2.8v decoupling caps). 5. v pp , 6.5v, is used for programming otpm. this pad is left unconnected if otpm is not being programmed. 6. v dd _1v8 can be combined with v dd _io, if v dd _io = 1.8v. data_p data_n data2_p data2_n data3_p data3_n data4_p data4_n clk_p clk_n 4 v aa (analog) 7 v dd 1v2 (digital) 1.2v v dd _io (i/o) 2.8v or 1.8v 2,3 1.5k 2 1.5k s clk s data extclk (6 C 27mhz) gpio [1:0] gpi [3:2] xshutdown 8 atest d gnd vcm_gnd vcm_isink 5 v pp (otpm write) (only connected while programming otpm) to hispi/mipi host interface vcm two-wire serial interface general purpose input/output a gnd v aa , v aa _pix 2.8v 10 f 1 f 0.1 f v dd _io v dd 1.2v 1.0 f 0.1 f v dd _1v8 1.8v 6 v dd 1v8 (otpm read) 2.8v 7 v dd _phy 1.2v gndphy gnd_io 0.1 f 4 v aa _pix 8 test 1 f 10 f 0.1 f 1.2v/0.4v v dd slvs_phy (h i sp i only )
ar0835hs_ds rev. d pub. 5/15 en 9 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor signal descriptions 7. v dd _1v2 and v dd _phy can be tied together. 8. hispi mode only: v dd slvs_phy is set to 0.4v ex ternally. alternatively, v dd slvs_phy may be tied to 1.2v if the user chooses to have the hispi slvs phy tx voltage sup- plied using the ar0835hs's inte rnal 1.2v-to-0.4v regulator. 9. register 31be[2:3] can be used to program the option of internal of external regulator, on semiconductor recommends using external regulator 10. atest can be left floating. 11. test pin must be tied to d gnd . 12. v dd _1v8 is the otpm read voltage. signal descriptions ar0835hs has 66 pads placed in a two-sided pad frame. it has only serial outputs. the part may be configured as hispi with different bit depths. the pad description is tabu- lated in table 4: table 4: pad descriptions pad name pad type description sensor control extclk input master clock input; pll input clock. 6 mhz - 27 mhz. this is a smia-compliant pad. gpio0 input/output general input an d one output function include: a. (default output) flash b. (input) all options in gpi2 high-z before xshutdown going high; default value is 0 after all three voltages in place and xshutdown being high. after reset, this pad is not powered down since its default use is as flash pin. if not used, can be left floating. gpio1 input/output general input and 2 output functions include: a. (default output) shutter b. (output) 3-d daisy chain communication output c. (input) all options in gpi2 high-z before xshutdown going high; default value is 0 after all three voltages in place and xshutdown being high. after reset, this pad is not powered-do wn since its default use is as shutter pin. if not used, can be left floating. gpi2 input general input; after reset, these pads are powered down by default; this means that it is not necessary to bo nd to these pads. functions include: a. s addr , switch to the second two-wire serial interface device address (see slave address/data direction byte on page 17) b. trigger signal for slave mode c. standby if not used, can be left floating. gpi3 input general input; after reset, these pads are powered-down by default; this means that it is not necessary to bo nd to these pads. functions include: a. 3-d daisy chain communication input b. all options in gpi2 if not used, can be left floating. two-wire serial interface s clk input serial clock for access to control and status registers.
ar0835hs_ds rev. d pub. 5/15 en 10 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor signal descriptions there are standard gpi and gpio pads, 2 each. chip can also be communicated to through the two-wire serial interface. the chip has four unique power supply requirements: 1.2 v (digital), 1.8 v, 2.8 v, and an analog 1.2 v or 0.4 v. these are further divi ded and in all there are seven power domains and five independent ground do mains from the esd perspective. s data i/o serial data for reads from and writes to control and status registers. serial output data[4:1]p output differential serial data (positive). data[4:1]n output differential serial data (negative). clk_p output differential serial clock/strobe (positive). clk_n output differential serial clock/strobe (negative). xshutdown input asynchronous active low reset. when asserted, data output stops and all internal registers are restored to their factory default settings. this pin will turn off the digital power domain and is the lowest power state of the sensor. vcm driver vcm_isink input/output vcm driver current sink output. if not used, it could be left floating. vcm_gnd input/output ground connection to vcm driv er. if not used, needs to be connected to ground (d gnd ). this ground must be separate from the other grounds. power v pp supply high-voltage pin for programming ot pm, present on sensors with that capability. this pin can be left floating during normal operation. v aa , v aa _pix, v dd _1v2_[v dd sw, v dd _ana, v dd _pll], v dd _1v8, v dd _io, v dd _phy, v dd slvs_phy, a gnd , pixgnd, d gnd supply power supply. the domains are specified in the next table. the brackets indicate the number of individual pins. v dd slvs_phy is for hispi mode only. table 5: independent power and ground domains pad name power supply description grounds d gnd 0v digital vcm_gnd 0v a gnd , pixgnd 0v analog power v aa 2.8v analog v aa _pix 2.8v pixel v dd slvs_phy 0.4v or 1.2v hispi phy. (hispi mode only) v dd sw, v dd _ana, v dd _ pll 1.2v digital v dd _io 1.8v/2.8v io v dd _phy 1.2v hispi/mipi v dd _1v8 1.8v otpm table 4: pad descriptions (continued) pad name pad type description
ar0835hs_ds rev. d pub. 5/15 en 11 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor system states system states the system states of the ar0835hs are represented as a state diagram in figure 4 and described in subsequent sections. the sensor's operation is broken down into three separate states: hardware standby, software standby, and streaming. the tran sition between these states might take a certain amount of clock cycles as outlined in figure 4 page 13 and figure 5 page 14. figure 4: system states streaming power on xshutdown = 0 timeout two-wire serial interface write: mode_select = 0 pll lock pll locked wait for frame end software standby two-wire serial interface write: mode_select = 1 two-wire serial interface write: software_reset = 1 internal initialization hardware standby extclk cycles xshutdown = 1 pll not locked power supplies turned off (asychronous from any state) frame in progress streaming powered off
ar0835hs_ds rev. d pub. 5/15 en 12 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor sensor initialization sensor initialization power-on sequence ar0835hs has four voltage supplies divided into several domains. the four voltages are 1.2 v (digital), 1.8 v, 2.8 v, and analog 1.2 v or 0.4 v. for proper operation of the chip, a power-up sequence is recommended as shown in figure 5. the power sequence is governed by controlled vs controlling behavior of a power supply and the inrush current (i.e. current that exists when not all power supplies are present). since v dd _io supply controls the xshutdown, it should be turned on first. the sequence of powering up the other two doma ins is not too critical. while turning on 2.8 v supply before 1.2 v supply shouldn't be an issue as shown in table 1, it is still not recommended since the 2.8 v domain is contro lled by 1.2 v signals. the dedicated 1.8 v domain is used only for otpm read function, so can turn on along with 1.8 v supply. due to the above considerations, the suggested power-on sequence is as shown in figure 5 on page 13: table 6: inrush consideration xshutdown 1.2v 1.8v (v dd io) 2.8v comment x present absent absent not supported x absent present absent supported x absent absent present supported x present present absent supported x present absent present not supported x absent present present supported 0 present present present powered down state 1 present present present powered up state
ar0835hs_ds rev. d pub. 5/15 en 13 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor power-on sequence figure 5: recommended power-up sequence table 7: power-up sequence definition symbol minimum typical maximum unit v dd _io to v dd _1v8 t 1 CC500 ms v dd _1v8 to v dd _1v2 t 2 0.2 C 500 ms v dd _1v2 to v aa t 3 0.2 C 500 ms active hard reset t 4 1C500 ms internal initialization t 5 2400 C C extclks pll lock time t 6 1C 5 ms v dd _io, v dd _slvs xshutdown s data s clk first serial write t 1 t 4 t 5 t 6 t 2 hard reset internal init soft standby pll lock streaming t 3 v dd _1v8 v dd _1v2, v dd _1v2_phy v aa , v aa _pix extclk
ar0835hs_ds rev. d pub. 5/15 en 14 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor power down sequence power down sequence the recommended power-down sequence for the ar0835hs is shown in figure 6. the three power supply domains (1.2 v, 1.8 v, and 2.8 v) must have the separation specified below. 1. disable streaming if output is acti ve by setting standby r0x301a[2] = 0. 2. after disabling the internal clock extclk, disable xshutdown. 3. after xshutdown is low disable the 2.8 v/1.8 v supply. 4. after the 2.8 v/1.8 v supply is low disable the 1.2 v supply. 5. after the 1.2 v supply is low disable the v dd _io supply. figure 6: recommended power-down sequence table 8: power-down sequence definition symbol minimum typical maximum unit extclk inactive to xshutdown active 100 C C ? s xshutdown to v aa t 0 200 C C ? s v aa to v dd _1v2 t 1 0CC ? s v dd _1v2 to v dd _1v8 t 2 0CC ? s v dd _1v8 to v dd _io t 3 0CC ? s xshutdown s clk s data t 0 t 2 t 1 turn off power supplies hard reset soft standby streaming focal planes deactivation v aa , v aa _pix v dd_ io, v dd_ slvs extclk v dd _1v8 v dd _1v2, v dd _1v2_phy t 3
ar0835hs_ds rev. d pub. 5/15 en 15 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor power down sequence hard standby and hard reset the hard standby state is reached by the as sertion of the xshutdown pad (hard reset). register values are not retained by this action, and will be returned to their default values once hard reset is completed. the minimum power consumption is achieved by the hard standby state. the details of the sequence are described below and shown in figure 7. 1. disable streaming if output is active by setting mode_select 0x301a[2] = 0. 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. assert xshutdown (active low) to reset the sensor. 4. the sensor remains in hard standby state if xshutdown remains in the logic ?0? state. figure 7: hard standby and hard reset soft standby and soft reset the ar0835hs can reduce power consumption by switching to the soft standby state when the output is not needed. register values are retained in the soft standby state. the details of the sequence are described below and shown in figure 8 on page 16. soft standby 1. disable streaming if output is active by setting mode_select 0x301a[2] = 0. 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. soft reset 1. follow the soft standby sequence list above. 2. set software_reset = 1 (r0x3021) to start the internal initialization sequence. 3. after 2400 extclks , the internal initializa tion sequence is completed and the current state returns to soft standby automatically. extc lk mode_select r0x0100 xshutdown logic 1 logic 0 streaming soft standby hard standby hard reset next row/frame
ar0835hs_ds rev. d pub. 5/15 en 16 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor power down sequence figure 8: soft standby and soft reset ex tcl k mode_select r0x0100 software_reset r0x0103 logic 1 logic 0 streaming soft standby soft reset soft standby next row/frame logic 0 logic 1 logic 0 480 2400 extclks
ar0835hs_ds rev. d pub. 5/15 en 17 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor two-wire serial register interface two-wire serial register interface a two-wire serial interface bus enables read/w rite access to control and status registers within the ar0835hs. the two-wire serial in terface is fully comp atible with the i 2 c stan- dard. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize transfers. data is transferred between the master and the slav e on a bidirectional signal (s data ). s data is pulled up to v dd off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in the two-wire seri al interface specific ation allow the slave device to drive s clk low; the ar0835hs uses s clk as an input only and therefore never drives it low. the electrical and timing specifications are further detailed on ?two-wire serial register interface? on page 17. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released wi th a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is defined as a low-to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. alter- nate slave addresses of 0x6e(write address) and 0x6f(read address) can be selected by enabling and asserting the s addr signal through the gpi pad.
ar0835hs_ds rev. d pub. 5/15 en 18 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor two-wire serial register interface the alternate slave addresses can al so be programmed through r0x31fc. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transf er. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence . the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same wa y as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s inte rnal register address is automatically incre- mented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
ar0835hs_ds rev. d pub. 5/15 en 19 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor two-wire serial register interface single read from random location this sequence (figure 9 on page 19) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates the write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master terminates the read by generating a no- acknowledge bit followed by a stop condition. figure 9 shows how the internal register address maintained by the ar0835hs is loaded and incremented as the sequence proceeds. figure 9: single read from random location single read from current location this sequence (figure 10) performs a read using the current value of the ar0835hs internal register address. the master terminates the read by generating a no-acknowl- edge bit followed by a stop condition. the figure shows two independent read sequences. figure 10: single read from current location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+ 1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a
ar0835hs_ds rev. d pub. 5/15 en 20 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor two-wire serial register interface sequential read, start from random location this sequence (figure 11) starts in the same way as the single read from random loca- tion (figure 9). instead of generating a no-ackno wledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 11: sequential read, start from random location sequential read, start from current location this sequence (figure 12) starts in the same way as the single read from current loca- tion (figure 10 on page 19). instead of gener ating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 12: sequential read, start from current location single write to random location this sequence (figure 13) begins with the ma ster generating a start condition. the slave address/data direction byte signals a writ e and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 13: single write to random location slave address 0 s sr a reg address[15:8] read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 read data read data m+l-2 m+l-1 m+l a p a a a a read data read data previous reg address, n n+1 n+2 n+l-1 n+ l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a reg address[7:0] a p previous reg address, n reg address, m m+1 a a write data
ar0835hs_ds rev. d pub. 5/15 en 21 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor two-wire serial register interface sequential write, start at random location this sequence (figure 14) starts in the same way as the single write to random location (figure 13). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the writ e is terminated by the master generating a st op condition. figure 14: sequential write, start at random location slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data
ar0835hs_ds rev. d pub. 5/15 en 22 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor registers registers the ar0835hs provides a 16-bit register addr ess space accessed through a serial inter- face (?two-wire serial register interface? on page 17). each register location is 8 or 16 bits in size. the address space is divided into the five major regions shown in table 9. the remainder of this section describes these registers in detail. register notation the underlying mechanism for reading and wr iting registers provides byte write capa- bility. however, it is convenient to consider some registers as multiple adjacent bytes. the ar0835hs uses 8-bit, 16-bit, and 32-bit regi sters, all implemented as 1 or more bytes at naturally aligned, contiguous locations in the address space. in this document, registers are described either by address or by name. when registers are described by address, the size of the regi sters is explicit. for example, r0x3024 is a 2-bit register at address 0x3024, and r0x3000 ? 1 is a 16-bit register at address 0x3000? 0x3001. when registers are described by name, th e size of the register is implicit. it is necessary to refer to the register table to determine that model_id is a 16-bit register. register aliases a consequence of the internal architecture of the ar0835hs is that some registers are decoded at multiple addresses. some registers in ?configuration space? are also decoded in ?manufacturer-specific space.? to provide unique names for all registers, the name of the register within manufacturer-specific register space has a trailing underscore. for example, r0x0202 is coarse_integration_time and r0x3012 is coarse_integration_time_. the effect of reading or writing a register through any of its aliases is identical. bit fields some registers provide control of several different pieces of related functionality, and this makes it necessary to refer to bit fields within registers. as an example of the nota- tion used for this, the least significant 4 bits of the chip_version_reg register are referred to as chip_version_reg[3:0] or r0x0000 ? 1[3:0]. bit field aliases in addition to the register aliases described above, some register fields are aliased in multiple places. for example, r0x0100 (mode_select) has only one operational bit, r0x0100[0]. this bit is aliased to r0x301a?b[2]. the effect of reading or writing a bit field through any of its aliases is identical. table 9: address space regions address range description 0x0000C0x0fff configuration registers (rea d-only and read-write dynamic registers) 0x1000C0x1fff parameter limit registers (read-only static registers) 0x2000C0x2fff image statistics registers (none currently defined) 0x3000C0x3fff manufacturer-specific registers (read-only and read-write dynamic registers)
ar0835hs_ds rev. d pub. 5/15 en 23 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor registers byte ordering registers that occupy more than one byte of address space are shown with the lowest address in the highest-order byte lane to match the byte-ordering on the data bus. for example, the chip_version_reg register is r0x0000 ? 1. in the register table the default value is shown as 0x4b00. this means that a read from address 0x0000 would return 0x4b, and a read from address 0x0001 would re turn 0x00. when reading this register as two 8-bit transfers on the serial interface, th e 0x4b will appear on the serial interface first, followed by the 0x00. address alignment all register addresses are aligned naturally. re gisters that occupy 2 bytes of address space are aligned to even 16-bit addresses, and registers that occupy 4 bytes of address space are aligned to 16-bit addresses th at are an integer multiple of 4. bit representation for clarity, 32-bit hex numbers are shown wi th an underscore between the upper and lower 16 bits. for example: 0x3000_01ab. data format most registers represent an unsigned binary value or set of bit fields. for all other register formats, the format is stated explicitly at th e start of the register description. the nota- tion for these formats is shown in table 10. register behavior registers vary from ?read-only,? ?read/write,? and ?read, write-1-to-clear.? double-buffered registers some sensor settings cannot be changed duri ng frame readout. for example, changing r0x3004?5 (x_addr_start) partway through frame readout would result in inconsistent row lengths within a frame. to avoid this, the ar0835hs double-buffers many registers by implementing a ?pending? and a ?live? ve rsion. reads and writes access the pending register. the live register co ntrols the sensor operation. the value in the pending register is transferre d to a live register at a fixed point in the frame timing, called frame start. frame start is defined as the point at which the first dark row is read out internally to the sensor . in the register tables the ?frame sync?d? column shows which registers or register fields are double-buffered in this way. table 10: data formats name description fix16 signed fixed-point, 16-bit number: tw os complement number, 8 fractional bits. examples: 0x0100 = 1.0, 0x8000 = C128, 0xffff = C0.0039065 ufix16 unsigned fixed-point, 16-bit number: 8. 8 format. examples: 0x0100 = 1.0, 0x280 = 2.5 flp32 signed floating-point, 32-bit number: ieee 754 format. exampl e: 0x4280_ 0000 = 64.0
ar0835hs_ds rev. d pub. 5/15 en 24 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor registers using grouped_parameter_hold register grouped_parameter_hold (r0x301a[15] ) can be used to inhibit transfers from the pending to the live registers. when the ar0835hs is in streaming mode, this register should be written to ?1? before making changes to any group of registers where a set of changes is required to take effect simultaneous ly. when this register is written to ?0,? all transfers from pending to live registers take place on the next frame start. an example of the consequences of failing to set this bit follows: an external auto exposure algorithm might want to change both gain and integration time between two frames. if the next frame starts between these operations, it will have the new gain, but not the new integration time, which would return a frame with the wrong brightness that might lead to a f eedback loop with the ae algorithm result- ing in flickering. bad frames a bad frame is a frame where all rows do no t have the same integration time or where offsets to the pixel values have changed during the frame. many changes to the sensor register settings can cause a bad frame. for example, when line_length_pck (r0x300c) is changed, the ne w register value does not affect sensor behavior until the next frame start. however, the frame that would be read out at that frame start will have been integrated using th e old row width, so reading it out using the new row width would result in a frame with an incorrect integration time. by default, bad frames are masked. if the ma sked bad frame option is enabled, both lv and fv are inhibited for these frames so that the vertical blanking time between frames is extended by the frame time. in the register tables, the ?bad frame? column shows where changing a register or register field will cause a bad frame. this notation is used: n?no. changing the register value will not produce a bad frame. y?yes. changing the register value might produce a bad frame. ym?yes; but the bad frame will be masked out when mask_corrupted_frames (r0x301a[9]) is set to ?1.? changes to integration time if the integration time is changed while fv is asserted for frame n , the first frame output using the new integration time is frame (n + 2) . the sequence is as follows: 1. during frame n , the new integration time is held in the pending register. 2. at the start of frame ( n + 1 ), the new integration time is tr ansferred to the live register. integration for each row of frame ( n + 1 ) has been completed using the old integration time. 3. the earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame ( n + 1 ). the actual time that rows start integrating using the new integration time is dependent upon the new value of the integration time. 4. when frame ( n + 2 ) is read out, it will have been integrated using the new integration time. if the integration time is changed on successive frames, each value written will be applied for a single frame; the latency betwee n writing a value and it affecting the frame readout remains at two frames.
ar0835hs_ds rev. d pub. 5/15 en 25 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor clocking changes to gain settings usually, when the gain settings are changed, the gain is updated on the next frame start. when the integration time and the gain are ch anged at the same time, the gain update is held off by one frame so that the first fram e output with the new integration time also has the new gain applied. in this case, a new gain should not be set during the extra frame delay. there is an option to turn off the extra frame delay by setting extra_delay (r0x3018). clocking default setup gives a ph ysical 73.2 mhz internal clock fo r an external input clock of 24 mhz. the sensor contains a phase-locked loop (p ll) for timing generation and control. the pll contains a prescaler to divide the input clock applied on extclk, a vco to multiply the prescaler output, and a set of dividers to generate the output clocks. the pll struc- ture is shown in figure 15 on page 26.
ar0835hs_ds rev. d pub. 5/15 en 26 ?semiconductor components industries, llc, 2015 ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor figure 15: clocking configuration (pll) figure 15 shows the different clocks and the names of the r egisters that contain or are used to control their values. the vt_pix_clk is divided by two to compensate for the fact that the design has 2 digital data paths. this divider should always remain turned on. ar0835hs has 10-to-8 compression. the usage of the output clocks is shown below: ? clk_pixel (vt_pix_clk / row_speed[2:0]) is used by the sens or core to readout and control the timing of the pixel array. the sensor core produces one 10-bit pixel each vt_pix_clk period. the line length (line_length_pck) is controlled in increments of the clk_pixel period. ? clk_op (op_pix_clk / row_speed[10:8]) is used to load parall el pixel data from the output fifo (see figure 40 on page 52) to the serializer. the output fifo generates one pixel each op_pix_clk period. pll _m ultiplie r(r0x306) (even number of 32-255 max vco freq is 1000mhz) pll multiplier (m) pll internal vco frequency op _ sys_clk op sys clk divider op pix clk divider op _ pix _clk clk _ op divider clk_op row_speed(r0x3016[10:8]) (1, 2, 4) op_pix_clk_div (r0x308) (8, 10) op_sys_clk_div (r0x30a) (1, 2, 4, 6, 8, 10, 12, 14, 16) extclk (6 to 27 mhz) pre pll divider (n +1) external input clock pll input clock pll _ ip _ clk _ freq (4-24 mhz) pre_pll_clk_div (r0x304) (1 to 64) (1 must only be used with even pll_multiplier values) clk _ pixel divider vt_ pix _clk row_speed (r0x 3016[2:0]) (1,2,4) vt_ sys _c lk vt sys clk divider (max freq (450 mhz)) vt pix clk divider clk_pixel vt_pix_clk_div (r0x300) (4 to 16, 3 with 3064[13]=0) vt_sys_clk_div (r0x302) (1, 2, 4, 6, 8, 10, 12, 14, 16)
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor ar0835hs_ds rev. d pub. 5/15 en 27 ?semiconductor components industries, llc, 2015. ? op_sys_clk is used to generate the serial data stream on the output. the relationship between this clock frequency and the op_pix_clk frequency is dependent upon the output data format. the pixel frequency can be calculated in general as: (eq 1) the output clock frequency can be calculated as: (eq 2) (eq 3) pll clocking the pll divisors should be programmed whil e the ar0835hs is in the software standby state. after programming the divisors, it is ne cessary to wait for the vco lock time before enabling the pll. the pll is enabled by entering the streaming state. an external timer will need to delay the entr ance of the streaming mode by 1 millisecond so that the pll can lock. the effect of programming the pll divisors while the ar0835hs is in the streaming state is undefined. clock control the ar0835hs uses an aggressive clock-gati ng methodology to reduce power consump- tion. the clocked logic is divided into a number of separate domains, each of which is only clocked when required. when the ar0835hs enters a soft standby stat e, almost all of the internal clocks are stopped. the only exception is that a small amount of logic is clocked so that the two- wire serial interface continues to respond to read and write requests. pixel clock mhz = ext_clk_freq_mhz pll_multiplier ? pre_pll_clk_div vt_sys_clk_div ? 2 ? vt_pix_clk_div ? row_speed[2:0] ? ------------------ ---------------------- ----------------- ------------------ ------------------ ----------------- ----------------- --------------- ------------------ -------------- clk_op_freq_mhz = ext_clk_freq_mhz pll_multiplier ? pre_pll_clk_div op_sys_clk_div ? op_pix_clk_div ? row_speed[10:8] ? ------------------- ---------------------- ----------------- ------------------ ------------------ ----------------- ---------------- ---------------- ------------------ ---------- op_sys_clk_freq_mhz = ext_clk_freq_mhz pll_multiplier ? pre_pll_clk_div op_sys_clk_div ? ----------------- ------------------ ----------------- ------------------ --------------
ar0835hs_ds rev. d pub. 5/15 en 28 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor features features interlaced hdr readout the sensor enables hdr by outputting frames where even and odd row pairs within a single frame are captured at different integr ation times. this output is then matched with an algorithm designed to reconstruct th is output into an hdr still image or video. the sensor hdr is controlled by two shut ter pointers (shutter pointer1, shutter pointer2) that control the integration of the odd (shutter pointer1) and even (shutter pointer 2) row pairs. figure 16: hdr integration time tint 1 tint 2 sample pointer shutter pointer 1 shutter pointer 2 i-frame 1 i-frame 2 output frame from sensor exposure i-frame 1 exposure i-frame 1 output i-frame 1 and 2
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 29 ?semiconductor components industries, llc, 2015. integration time for interlaced hdr readout tint1 (integration time 1) an d tint2 (integration time 2) the limits for the coarse integration time are defined by: (eq 4) (eq 5) the actual integratio n time is given by: (eq 6) (eq 7) if this limit is broken, the frame ti me will automatically be extended to (coarse_integration_time + coar se_integration_time_max_margin) to accommodate the larger integration time. the ratio between even and odd rows is ty pically adjusted to 1x, 2x, 4x, and 8x. coarse_integration_time_mi n coarse_integration_time ? frame_length_lines coarse_i ntegration_time_max_margin ? ?? ? coarse_integration_time2_m in coarse_integration_time2 ? frame_length_lines coarse_int egration_time2_max_margin ? ?? ? integration_time coarse_integration_time line_length_pck ? ?? vt_pix_clk_freq_mhz 10 6 ? -------------------- --------------------- ------------------ ------------------ ----------------- -------------- = integration_time2 coarse_integration_time2 line_length_pck ? ?? vt_pix_clk_freq_mhz 10 6 ? -------------------- --------------------- ------------------ ------------------ ----------------- ----------------- =
ar0835hs_ds rev. d pub. 5/15 en 30 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout bayer resampler the imaging artifacts found from a 2x2 binning or summing will show image artifacts from aliasing. these can be corrected by resampling the sampled pixels in order to filter these artifacts. figure 17 shows the pixel location resulting from 2x2 summing or binning located in the middle and the resulting pixel locations after the bayer re- sampling function has been applied. figure 17: bayer resampling the improvements from using the bayer resampling feature can be seen in figure 18. in this example, image edges seen on a diagonal have smoother edges when the bayer re- sampling feature is applied. this feature is only designed to be used with modes config- ured with 2x2 binning or summing. the feature will not remove aliasing artifacts that are caused skipping pixels. figure 18: results of resampling to enable the bayer resampling feature: 1. set r0x400 = 2 // enable the on-chip scalar. 2. set r0x306e to 0x90b0 // configure the on-chip scalar to resample bayer data. to disable the bayer resampling feature: 1. set r0x400 = 0 // disable the on-chip scalar. 2. set r0x306e to 0x9080 // configure the on-chip scalar to resample bayer data. note: the image readout (rows and columns) has to have two extra rows and two extra col- umns when using the resample feature. figure 19: illustration of resampling operation 2x2 binned - before 2x2 binned - after resampling image array readout 3264 x 2448 image size output 1632 x 1224 resampled image output 1632 x 1224 2 x 2 binning resampling
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 31 ?semiconductor components industries, llc, 2015. one-time programmable memory (otpm) the ar0835hs features 5.6 kbits of one-time programmable memory (otpm) for storing shading correction coefficients, individual module, and customer-specific information. the user may program the data before shipping. otpm can be accessed through two- wire serial interface. the ar0835hs uses the auto mode for fast otpm programming and read operations. to read out the otpm, 1.8v supply is required. as a result, a dedicated dv dd _1v8 pad has been implemented.during the programming process, a dedicated pin for high voltage needs to be provided to perform the anti-fusing operation. this voltage (v pp ) would need to be 6.5v. the completion of the programming process will be communi- cated by a register through th e two-wire serial interface. if the v pp pin does not need to be bonded out as a pin on the module, it should be left floating inside the module. the programming of the otpm requires the se nsor to be fully powered and remain in software standby with its clock input applied. the information will be programmed through the use of the two-wire serial interf ace, and once the data is written to an internal register, the programming host ma chine will apply a high voltage to the programming pin, and send a program command to initiate the anti-fusing process. after the sensor has finished programming the otpm, a status bit will be set to indicate the end of the programming cycle, and the host machine can poll the setting of the status bit through the two-wire serial interf ace. only one programming cycle for the 16- bit word can be performed. reading the otpm data requires the sensor to be fully powered and operational with its clock input applied. the data can be read th rough a register from the two-wire serial interface. programming and verifying the otpm the procedure for programming and ve rifying the ar0835hs otpm follows: 1. apply power to all the power rails of the sensor. 2. provide a 12-mhz extclk clock input. 3. set r0x301a = 0x18, to put sensor in the soft standby mode. 4. set r0x3130 = 0xff01 (timing configuration) 5. set r0x304c[15:8] = record type (e.g. 0x30) 6. set r0x304c[7:0] = length of the record which is the number of otpm data registers that are filled in. 7. set r0x3054[9] = 0 to ensure that the error checking and correction is enabled. 8. write data into all the otpm data registers: r0x3800-r0x39fe. 9. ramp up vpp to 6.5v. 10. set the otpm_control_auto_wr _start bit in the otpm_control register r0x304a[0] = 1, to initiate the auto program sequence. the sensor will now program the data into the otpm. 11. poll otpm_control_auto_wr_e nd (r0x304a [1]) to determine when the sensor is fin- ished programming the word. 12. verify that the otpm_control_aut o_wr_success(0x304a [2]) bit is set. 13. if the above bits are not set to 1, then examine otpm_status register r0x304e[9] to ver- ify if the otpm memory is full and 0x304e[1 0] to verify if otpm memory is insuffi- cient. 14. remove the high voltage (v pp ) and float v pp pin.
ar0835hs_ds rev. d pub. 5/15 en 32 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout reading the otpm 1. apply power to all the power rails of the sensor (v dd _io, v aa , v aa _pix, dv dd _1v2, dv dd _1v2_phy, and dv dd _1v8) at their nominal voltage. 2. set extclk to normal operating frequency. 3. perform proper reset sequence to the sensor. 4. set r0x3134=0xcd95 (timing configuration) 5. set r0x304c[15:8] = record type (for example, 0x30) 6. set r0x304c[7:0] = length of the record which is the number of data registers to be read back. this could be set to 0 during otpm auto read if length is unknown. 7. set r0x3054 = 0x0400 8. initiate the auto read sequence by se tting the otpm_control_auto_read_start bit (r0x304a[4]) = 1. 9. poll the otpm_control_auto_rd_end bit (r0x 304a[5]) to determine when the sensor is finished reading the word(s). when this bit becomes 1, the ot pm_control_auto_rd_- success bit (r0x304a[6]) will indicate whethe r the memory was read successfully or not. 10. data can now be read back from th e otpm_data registers (r0x3800-r0x39fe). image acquisition modes the ar0835hs supports two image acquisition modes: 1. electronic rolling shutter (ers) mode. this is the normal mode of operation. wh en the ar0835hs is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when the ers is in use, timing and control logic wi thin the sensor sequen ces through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate inci- dent light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is fixed, leading to a uniform integration time across the frame. when the integration time is changed (by using the two- wire serial interface to change register settings), the timing and control logic contro ls the transition from old to new integra- tion time in such a way that the stream of output frames from the ar0835hs switches cleanly from the old integration time to the new while only generating frames with uniform integration. see ?changes to integration time? on page 24. 2. global reset release (grr) mode. this mode can be used to acquire a single image at the current resolution. in this mode, the end point of the pixel integration ti me is controlled by an external electro- mechanical shutter, and the ar0835hs provid es control signals to interface to that shutter. the operation of this mode is de scribed in detail in ?global reset release (grr)? on page 46. the benefit for the use of an external electr omechanical shutter is that it eliminates the visual artifacts associated with ers operatio n. visual artifacts arise in ers operation, particularly at low frame rates, because an ers image effectively integrates each row of the pixel array at a different point in time. window control the sequencing of the pixel array is contro lled by the x_addr_start, y_addr_start, x_ad- dr_end, and y_addr_end registers. the output image size is controlled by the x_output_- size and y_output_size registers.
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 33 ?semiconductor components industries, llc, 2015. pixel border the default settings of the sensor provide a 3264h x 2448v image. a border of up to 8 pixels (4 in binning) on each edge can be enabled by reprogramming the x_addr_start, y_addr_start, x_addr_end, y_addr_end, x_ou tput_size, and y_output_size registers accordingly. these border pixels can be used but are disabled by default. readout modes horizontal mirror the horizontal_mirror bit in the image_orientatio n register is set by default. the result of this is that the order of pixel readout within a row is reversed, so that readout starts from x_addr_end and ends at x_addr_start. figure 20 on page 33 shows a sequence of 6 pixels being read out with horizontal_mirror = 0 an d horizontal_mirror = 1. changing horizon- tal_mirror causes the bayer order of the outp ut image to change; the new bayer order is reflected in the value of the pixel_order register. figure 20: effect of horizontal_mirror on readout order vertical flip when the vertical_flip bit is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. figure 21 shows a sequence of 6 rows being read out with vertical_flip = 0 and vertical_flip = 1. changing vertical_flip causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register. figure 21: effect of vertical_flip on readout order subsampling the ar0835hs supports subsampling to reduce the amount of data processed by the signal chains in the ar0835hs, thereby allo wing the frame rate to be increased and power consumption reduced. subsampling is enabled by setting x_odd_inc and/or g0[ 9 :0] r0[9:0] g1[9:0] r1[9:0] g2[9:0] r2[9:0] r2[9:0] g2[9:0] r1[9:0] g1[9:0] r0[9:0] g0[9:0] line_valid horizontal_mirror = 0 d out [9:0] horizontal_mirror = 1 d out [9:0] row0[9:0] row1[9:0] row2[9:0] row3[9:0] row4[9:0] row5[9:0] row5[9:0] row4[9:0] row3[9:0] row2[9:0] row0[9:0] frame_valid vertical_flip = 0 d out [9:0] vertical_flip = 1 d out [9:0] row1[9:0]
ar0835hs_ds rev. d pub. 5/15 en 34 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout y_odd_inc. values of 1, 3, and 7 can be supported. setting both of these variables to 3 reduces the amount of row and column data processed and is equivalent to the 2 x 2 skipping readout mode provided by the ar0835hs. setting x_odd_inc = 3 and y_odd_inc = 3 results in a quarter reduction in output image size. figure 22 on page 34 shows a sequence of 8 columns being read out with x_odd_inc = 3 and y_odd_inc = 1. figure 22: effect of x_odd_inc = 3 on readout sequence a 1/16 reduction in resolution is achieved by setting both x_odd_inc and y_odd_inc to 7. this is equivalent to 4 x 4 skipping readout mode provided by the ar0835hs. figure 23 shows a sequence of 16 columns being read out with x_odd_inc = 7 and y_odd_inc = 1. figure 23: effect of x_odd_inc = 7 on readout sequence the effect of the different subsampling settin gs on the pixel array readout is shown in figure 24 through figure 26 on page 36. g0[9:0] r0[9:0] g1[9:0] r1[9:0] g2[9:0] r2[9:0] g3[9:0] r3[9:0] g0[9:0] r0[9:0] g2[9:0] r2[9:0] line_valid x_odd_inc = 1 d out [9:0] line_valid x_odd_inc = 3 d out [9:0] g0[9:0] r0[9:0] g1[9:0] r1[9:0] g2[9:0] g7[9:0] r7[9:0] g0[9:0] r0[9:0] g4[9:0] r4[9:0] line_valid x_odd_inc = 1 d out [9:0] line_valid x_odd_inc = 7 d out [9:0] ...
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 35 ?semiconductor components industries, llc, 2015. figure 24: pixel readout (no subsampling) figure 25: skip2 pixel readout (x_odd_inc = 3, y_odd_inc = 3) x incrementing y incrementing x incrementing y incrementing
ar0835hs_ds rev. d pub. 5/15 en 36 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout figure 26: skip4 pixel readout (x_odd_inc = 7, y_odd_inc = 7) x incrementing y incrementing
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 37 ?semiconductor components industries, llc, 2015. programming restrictions when subsampling when subsampling is enabled and the sensor is switched back and forth between full resolution and subsampling, on semiconductor recommends that line_length_pck be kept constant between the two modes. this al lows the same integration times to be used in each mode. when subsampling is enabled, it may be ne cessary to adjust the x_addr_start, x_ad- dr_end, y_addr_start, and y_addr_end settings: the values for these registers are required to correspond with rows/columns that fo rm part of the subsampling sequence. the adjustment should be made in accordance with these rules: x_skip_factor = (x_odd_inc + 1) / 2 y_skip_factor = (y_odd_inc + 1) / 2 ? x_addr_start should be a multiple of x_skip_factor * 4 ? (x_addr_end - x_addr_start + x_odd_inc) should be a multiple of x_skip_factor * 4 ? (y_addr_end - y_addr_start + y_odd_inc) sh ould be a multiple of y_skip_factor * 4 the number of columns/rows read out with subsampling can be found from the equa- tion below: ? columns/rows = (addr_end - addr_start + odd_inc) / skip_factor table 11 shows the row or column address sequencing for normal and subsampled readout. in the 2x skip case, there are two possible subsampling sequences (because the subsampling sequence only reads half of the pixels) depending upon the alignment of the start address. similarly, there will be four possible subsampling sequences in the 4x skip case (though only the first two are shown in table 11). table 11: row address sequencing during subsampling odd_inc = 1 (normal) odd_inc = 3 (2x skip) odd_inc = 7 (4x skip) start = 0 start = 0 start = 0 000 111 2 3 44 55 6 7 888 999 10 11 12 12 13 13 14 15
ar0835hs_ds rev. d pub. 5/15 en 38 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout binning the ar0835hs supports 2 x 1 (column binning, also called x-binni ng). binning has many of the same characteristics as skipping, but because it gathers image data from all pixels in the active window (rather than a su bset of them), it achieves superior image quality and avoids the aliasing artifacts that can be a characte ristic side effect of skip- ping. binning is enabled by selectin g the appropriate subsampling settings (in read_mode, the sub-register x_odd_inc = 3 and y_odd_inc = 1 for x-binning and se tting the appropriate binning bit in read_mode r0x3040[11] = 1 fo r x_bin_enable). as with skipping, x_ad- dr_end and y_addr_end may require adjustment when binning is enabled. it is the first of the two columns/rows binned together that should be the end column/row in binning, so the requirements to the end address are exactly the same as in skipping mode. the effect of the different binning is shown in figure 27 below and figure 28 on page 39. binning can also be enabled when the 4x subsampling mode is enabled (x_odd_inc = 7 and y_odd_inc = 1 for x-binning, x_odd_inc = 7 and y_odd_inc = 7 for 4x xy-binning). in this mode, however, not all pixels will be used so this is not a 4x binning implementa- tion. an implementation providing a combination of skip2 and bin2 is used to achieve 4x subsampling with better imag e quality. the effect of this subsampling mode is shown in figure 28 on page 39. figure 27: bin2 pixel readout (x_odd_inc = 3, y_odd_inc = 1, x_bin = 1) x incrementing y incrementing
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 39 ?semiconductor components industries, llc, 2015. figure 28: bin2pixel readout (x_odd_inc = 3, y_odd_inc = 3, x_bin = 1) binning address sequencing is a bit more complicated than during subsampling only, because of the implementation of the binning itself. for a given column n , there is only one other column, n_bin, that can be binned with, because of physical limitations in the colu mn readout circuitry. the possible address sequences are shown in table 12. there are no physical limitations on what can be binned together in the row direction. a given row n will always be binned with row n+2 in 2x subsampling mode and with row n+4 in 4x subsampling mode. therefore, which rows get binned together depends upon the alignment of y_addr_start. the possible sequences are shown in table 13 on page 40. table 12: column address sequencing during binning odd_inc = 1 (normal) odd_inc = 3 (2x bin) odd_inc = 7 (2x skip + 2xbin) x_addr_start = 0 x_addr_start = 0 x_addr_start = 0 00/2 0/4 11/3 1/5 2 3 44/6 55/7 6 7 8 8/10 8/12 9 9/11 9/13 10 11 12 12/14 13 13/15 14 15 x incrementing y incrementing
ar0835hs_ds rev. d pub. 5/15 en 40 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout table 13: row address se quencing during binning odd_inc = 1 (normal) odd_inc = 3 (2x bin) odd_inc = 7 (2x skip + 2x bin) x_addr_start = 0 x_addr_start = 0 x_addr_start = 0 00/2 0/4 11/3 1/5 2 3 44/6 55/7 6 7 8 8/10 8/12 9 9/11 9/13 10 11 12 12/14 13 13/15 14 15
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 41 ?semiconductor components industries, llc, 2015. programming restrictions when binning and summing binning and summing require different sequ encing of the pixel array and impose different timing limits on the operation of the sensor. as a result, when xy-subsampling is enabled, some of the programming limits declared in the parameter limit registers are no longer valid. in addition, the default values for some of the manufacturer-specific registers need to be reprogrammed. see ?minimum frame time? and "minimum row time" on page 43. subsampling / binning options: 1. xskipyskip r0x3040[11], x_bin_en: 0 r0x3040[13], row_sum: 0 r0x0382: x_odd_inc = 3 (xskip2) or 7 (xskip4) r0x0386: y_odd_inc = 3 (yskip2), 7 (yskip4) or 15 (yskip8) 2. xbinyskip r0x3040[11], x_bin_en: 1 r0x3040[13], row_sum: 0 r0x0382: x_odd_inc = 3 (xbin2) r0x0386: y_odd_inc = 3 (yskip2), 7 (yskip4) or 15 (yskip8) 3. xskipysum r0x3040[11], x_bin_en: 0 r0x3040[13], row_sum: 1 r0x0382: x_odd_inc = 3 (xskip2) or 7 (xskip4) r0x0386: y_odd_inc = 3 (ysum2) 4. xbinysum r0x3040[11], x_bin_en: 1 r0x3040[13], row_sum: 1 r0x0382: x_odd_inc = 3 (xbin2) r0x0386: y_odd_inc = 3 (ysum2) 5. xsumysum r0x3040[11], x_bin_en: 1 r0x3040[13], row_sum: 1 r0x3ee4[0], sreg_colamp_sum2: 1 (cannot write to this bit when streamin g - have to write to entire register) r0x0382: x_odd_inc = 3 (xsum2) r0x0386: y_odd_inc = 3 (ysum2)
ar0835hs_ds rev. d pub. 5/15 en 42 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout binning, skipping, and summing mode summing, skipping, and binning can be co mbined in the modes listed in table 14. unlike binning mode where the values of adjacent same color pixels are averaged together, summing adds the pixel values together resulting in better sensor sensitivity. summing is supposed to provide two times the sensitivity compared to the binning only mode. figure 29: pixel binning and summing table 14: available skip, bin, and sum modes in the ar0835hs sensor subsampling method horizontal vertical skipping 2x, 4x 2x, 4x, 8x binning 2x summing 2x 2x 2 x2 binning o r summing summing avg avg x-binning v v h h
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 43 ?semiconductor components industries, llc, 2015. scaler scaling reduces the size of the output imag e while maintaining the same field-of-view. the input and output of the scaler is in bayer format. when compared to skipping, scaling is advant ageous as it avoids aliasing. the scaling factor, programmable in 1/16 steps, is us ed for horizontal and vertical scalers. the ar0835hs sensor is capable of horizontal scaling and full (horizontal and vertical) scaling. the scale factor is determined by: ? n, which is fixed at 16 ? m, which is adjustable with register r0x0404 ? legal values for m are 16 through 96, giving the user the ability to scale from 1:1 (m=16) to 1:6 (m=96). frame rate control the formulas for calculating the frame rate of the ar0835hs are shown below. the line length is programmed directly in pixel clock periods through register line_length_pck. for a specific window size, the minimum line length can be found from equation 8: (eq 8) note that line_length_pck also needs to m eet the minimum line length requirement set in register min_line_length_pck. the row time can either be limited by the time it takes to sample and reset the pixel array for each row, or by the time it takes to sample and read out a row. values for min_line_blanking_pck are provided in ?minimum row time? on page 43. the frame length is programmed directly in number of lines in the register frame_line_length. for a specific window size, the minimum frame length can be found in equation 9: (eq 9) the frame rate can be calculated from these variables and the pixel clock speed as shown in equation 10: (eq 10) if coarse_integration_time is set larger than frame_length_lines the frame size will be expanded to coarse_integration_time + 1. minimum row time enough time must be given to the output fifo so it can output all data at the set frequency within one row time. there are therefore two checks that must all be met when programming line_length_pck: minimum line_length_pck x_addr_end - x_addr_start 1 + subsampling factor ------------------- --------------------- ------------------ ----------------- - min_line_blanking_pck + ?? ?? = minimum frame_length_lines y_addr_end - y_addr_start 1 + subsampling factor -------------------- --------------------- ------------------ ---------------- - min_frame_blanking_lines + ?? ?? = frame rate vt_pixel_clock_mhz x 1 x 10 6 line_length_pck_x frame_length_lines ------------------ ---------------------- ----------------- ------------------ ----------------- - =
ar0835hs_ds rev. d pub. 5/15 en 44 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ? line_length_pck > min_line_length_pck in table 15. ? the row time must allow the fifo to output all data during each row. that is, line_length_pck > (x_output_size * 2 + 0x005e) * ?vt_pix_clk period? / ?op_pix_clk period? minimum frame time the minimum number of rows in the image is 1, so min_frame_length_lines will always equal (min_frame_blanking_lines + 1). integration time the integration (exposure) time of the ar08 35hs is controlled by the coarse_integra- tion_time register. the limits for the coarse integration time are defined by: coarse_integration_time_min < coarse_integration_time (eq 11) the actual integratio n time is given by: (eq 12) it is required that: coarse_integration_time ? (frame_length_lines ? coarse_integration_time_max_margin) (eq 13) if this limit is broken, the frame time will automatically be extended to (coarse_integra- tion_time + coarse_integartion_time_max_mar gin) to accommodate the larger integra- tion time. in binning mode, frame_length_lines should be set larger than coarse_integration_time by at least 3 to avoid column imbalance artifact. table 15: minimum frame time and blanking numbers min_frame_blanking_lines 0x008f min_frame_length_lines 0x0a1f integration_time coarse_integration_time * line_length_pck ?? vt_pix_clk_freq_mhz*10 6 ?? ---------------------------------------------------------------------------------------------------------- =
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 45 ?semiconductor components industries, llc, 2015. flash timing control the ar0835hs supports both xenon and led flash timing through the flash output signal. the timing of the flash signal with the default settings is shown in figure 30 (xenon) and figure 31 on page 45 (led). the flash and flash_count registers allow the timing of the flash to be changed. the flash can be programmed to fire only once, delayed by a few frames when asserted, and (f or xenon flash) the flash duration can be programmed. enabling the led flash will cause one bad frame, where several of the rows only have the flash on for part of their integration time. th is can be avoided either by first enabling mask bad frames (r0x301a[9] = 1) before the enabling the flash or by forcing a restart (r0x301a[1] = 1) immediately after enabling th e flash; the first bad frame will then be masked out, as shown in figure 31. read-only bi t flash[14] is set duri ng frames that are correctly integrated; the state of this bit is shown in figures 30 and figure 31. figure 30: xenon flash enabled figure 31: led flash enabled note: an option to invert the flash output signal through r0x3046[7] is also available. frame_ v alid flash strobe state of triggered bit (r0x3046-7[14]) bad frame is masked frame_valid flash strobe state of triggered bit (r0x3046-7[14]) flash enabled bad frame good frame good frame flash disabled during this frame is masked during this frame
ar0835hs_ds rev. d pub. 5/15 en 46 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout global reset release (grr) global reset release mode allo ws the integration time of the ar0835hs to be controlled by an external electromechanical shutter. grr mode is generally used in conjunction with ers mode. the ers mode is used to prov ide viewfinder informat ion, the sensor is switched into grr mode to capture a single frame, and the sensor is then returned to ers mode to restore viewfinder operation. overview of global reset release sequence the basic elements of the grr sequence are: 1. by default, the sensor operates in ers mo de and the shutter output signal is low. the electromechanical shutter must be open to allow light to fall on the pixel array. integration time is controlled by the coarse_integration_time register. 2. a global reset sequence is triggered. 3. all of the rows of the pixel array are placed in reset. 4. all of the rows of the pixel array are taken out of reset simultaneously. all rows start to integrate incident light. the electromechanical shutter may be open or closed at this time. 5. if the electromechanical shutter has been closed, it is opened. 6. after the desired integration time (contr olled internally or externally to the ar0835hs), the electromecha nical shutter is closed. 7. a single output frame is generated by th e sensor with the usual lv, fv, pixclk, and d out timing. as soon as the output frame has completed (fv negates), the electrome- chanical shutter may be opened again. 8. the sensor automatically resumes operation in ers mode. this sequence is shown in figure 32. the fo llowing sections expand to show how the timing of this sequ ence is controlled. figure 32: overview of global reset sequence ers ers row reset integration readout
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 47 ?semiconductor components industries, llc, 2015. entering and leaving the global reset sequence a global reset sequence can be triggered by a register write to r0x315e global_se- q_trigger[0] (global trigger, to transition this bit from a 0 to a 1) or by a rising edge on a suitably-configured gpi input). when a global reset sequence is triggered, the sensor waits for the end of the current row. when lv negates for that row, fv is negate d 6 pixclk periods later, potentially trun- cating the frame that was in progress. the global reset sequence completes with a frame readout. at the end of this readout phase, the sensor automatically resumes op eration in ers mode. the first frame inte- grated with ers will be generated after a delay of approximately ((13 + coarse_integra- tion_time) * line_length_pck). this sequence is shown in figure 33. while operating in ers mode, double-buffered registers (?double-buffered registers? on page 23) are updated at the start of each frame in the usual way. during the global reset sequence, double-buffered registers are up dated just before the start of the readout phase. figure 33: entering and leaving a global reset sequence programmable settings the registers global_rst_end and global_read_ start allow the duration of the row reset phase and the integration phase to be controll ed, as shown in figure 34. the duration of the readout phase is determined by the active image size. the recommended setting for global_rst_end is 0x3160 (for example, 512 ? s total reset time) with default vt_pix_clk. this allows suffic ient time for all rows of the pixel array to be set to the correct reset volt age level. the row reset phase ta kes a finite amount of time due to the capacitance of the pixel array an d the capability of the internal voltage booster circuit that is used to generate the reset voltage level. as soon as the global_rst_end count has expired, all rows in the pixel array are taken out of reset simultaneously and the pixel array begins to integrate incident light. figure 34: controlling the reset and integr ation phases of the global reset sequence ers ers row reset integration readout trigger wait for end of current row automatic at end of frame reado ut ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end global_read_start
ar0835hs_ds rev. d pub. 5/15 en 48 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout control of the electromechanical shutter figure 35 on page 48 shows two different wa ys in which a shutter can be controlled during the global reset sequence. in both cases, the maximum integration time is set by the difference between global_read_start and global_rst_end. in shutter example 1, the shutter is open during the initial ers sequence and during the row reset phase. the shutter closes during the integration phase. the pixel array is integrating incident light from the start of the integration phase to the point at which the shutter closes. finally, the shutter opens again after the end of th e readout phase. in shutter example 2, the shutter is open during the initial ers sequence and closes sometime during the row reset phase. the shutter both opens and clos es during the integration phase. the pixel array is integrating incident light for the pa rt of the integration phase during which the shutter is open. as for the previous example, the shutter opens again after the end of the readout phase. figure 35: control of the electromechanical shutter it is essential that the shutter remains clos ed during the entire row readout phase (that is, until fv has negated for the frame readout); otherwise, some rows of data will be corrupted (over-integrated). it is essential that the shutte r closes before the end of the integration phase. if the row readout phase is allowed to start before the shutter closes, each row in turn will be inte- grated for one row-time longer than the previous row. after fv negates to signal the completion of the readout phase, there is a time delay of approximately (10 * line_length_pck) before th e sensor starts to integrate light-sensitive rows for the next ers frame. it is essential that the shutter be opened at some point in this time window; otherwise, the first er s frame will not be uniformly integrated. the ar0835hs provides a shutter output sign al to control (or help the host system control) the electromechanical shutter. the timing of the shutter output is shown in figure 36 on page 49. shutter is negated by default. the point at which it asserts is controlled by the programming of global_shu tter_start. at the end of the global reset readout phase, shutter negates approximately (2 * line_length_pck) after the negation of fv. ers ers row reset integration readout trigger wait for end of curr ent row automatic at end of frame readout global_rst_end global_read_start maximum i ntegration time shutter open (physical) shutter open shutter closed actual integration time shutter open (physical) shutter open shutter closed closed shutter open actual integration time shutter example 1 shutter example 2
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 49 ?semiconductor components industries, llc, 2015. this programming restriction must be met for correct operation: ? global_read_start > global_shutter_start. figure 36: controlling the shutter output using flash with global reset if r0x315e global_seq_trigger[2] = 1 (global flash enabled) when a global reset sequence is triggered, the flash output signal will be pulsed during the integration phase of the global reset sequence. the flash output will assert a fixed number of cycles after the start of the integration phase and will remain a sserted for a time that is controlled by the value of the flash_count register. when flash_ count is programmed for value n, (where n is 0?0x3fe) the resulting flash duration is given by n * 512 * (1/vt_pix_clk_freq_mhz), as shown in figure 37. figure 37: using flash with global reset ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end global_read_start shutter (signal) global_shutter_start ~2*line_length_pck er s r o w re s et inte g rati o n rea dou t er s trigger wait for end of current row automatic at end of frame readout global_rst_end flash flash_count (fixed) global_read_start shutter global_ shutter_start ~2*line_length_pck
ar0835hs_ds rev. d pub. 5/15 en 50 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout when the flash_count = 0x3ff, the flash signal will be maximized and goes low when readout starts, as shown in figure 38 on page 50. this would be preferred if the latency in closing the shutter is longer than the latency for turning off the flash. this guarantees that the flash stays on while the shutter is open. figure 38: extending flash duration in global reset (reference readout start) external control of integration time if global_seq_trigger[1] = 1 (global bulb enabled) when a global reset sequence is trig- gered, the end of the integration phase is co ntrolled by the level of trigger (global_se- q_trigger[0] or the associated gpi input). this allows the integration time to be controlled directly by an input to the sensor. this operation corresponds to the shutter ?b ? setting on a traditional camera, where ?b? originally stood for ?bulb? (the shutter setting used for synchronization with a magne- sium foil flash bulb) and was later considered to stand for ?brief? (an exposure that was longer than the shutter coul d automatically accommodate). when the trigger is de-asserted to end integrat ion, the integration phase is extended by a further time given by global_read_start ? global_shutter_start . usually this means that global_read_start should be set to global_shutter_start + 1 . the operation of this mode is shown in figure 39 on page 51. the figure shows the global reset sequence being triggered by the gpi2 input, but it could be triggered by any of the gpi inputs or by the setting and subsequence clearing of the global_seq_trigger[0] under software control. the integration time of the grr sequence is defined as: (eq 14) where: er s r o w re s et inte g rati o n rea dou t er s trigger wait for end of current row automatic at end of frame readout global_rst_end flash (fixed) global_read_ start shutter global_ shutter_start ~2*line_length_pck integration time global _ scale [ global _ read _ start global _ shutter _ start ? global _ rst _ end ] ? ? vt _ pix _ clk _ freq _ mhz ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------- - =
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout ar0835hs_ds rev. d pub. 5/15 en 51 ?semiconductor components industries, llc, 2015. (eq 15) (eq 16) the integration equation allo ws for 24-bit precision when calculating both the shutter and readout of the image. the global_rst_end has only 16-bit as th e array reset function and requires a short amount of time. the integration time can also be scaled using global_scale. the variable can be set to 0?512, 1?2048, 2?128, and 3?32. these programming restrictions must be me t for correct operation of bulb exposures: ? global_read_start > global_shutter_start ? global_shutter_start > global_rst_end ? global_shutter_start must be smaller than the exposure time (that is, this counter must expire before the trigger is de-asserted) figure 39: global reset bulb retriggering the global reset sequence the trigger for the global reset sequence is edge-sensitive; the gl obal reset sequence cannot be retriggered until the global trig ger bit (in the r0x315e global_seq_trigger register) has been returned to ?0,? and the gp i (if any) associated with the trigger func- tion has been negated. the earliest time that the glob al reset sequence can be retriggered is the point at which the shutter output negates; this occurs ap proximately (2 * line_length_pck) after the negation of fv for the global reset readout phase. using global reset with smia data path when a global reset sequence is triggered, it usually results in the frame in progress being truncated (at the end of the current output line). the smia data path limiter func- tion (see figure 40 on page 52) attempts to extend (pad) all frames to the programmed value of y_output_size. if this padding is still in progress when the global reset readout phase starts, the smia data path will not de tect the start of the frame correctly. there- fore, to use global reset with the serial data path, this timing scenario must be avoided. one possible way of doing this would be to synchronize (under software control) the assertion of trigger to an end-of-frame marker on the serial data stream. at the end of the readout phase of the global reset sequence, the sensor automatically resumes operation in ers mode. global _ read _ start 2 16 global _ read _ start 27:0 ?? ? global _ read _ start 115:0 ?? + ?? = global _ shutter _ start 2 16 global _ shutter _ start 27:0 ?? ? global _ shutter _ start 115:0 ?? + ?? = ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end gpi2 global_read_start - global_shutter_start
ar0835hs_ds rev. d pub. 5/15 en 52 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor integration time for interlaced hdr readout the frame that is read out of the sensor duri ng the global reset readout phase has exactly the same format as any other frame out of th e serial pixel data interface, including the addition of two lines of embedded data. the value of the coarse_integration_time register within the embedded data matches the programmed values of those registers and does not reflect the integration time used during the glob al reset sequence. global reset and soft standby if the r0x301a[2] mode_select[stream] bit is cleared while a global reset sequence is in progress, the ar0835hs will remain in stream ing state until the global reset sequence (including frame readout) has completed, as shown in figure 40 on page 52. figure 40: entering soft standb y during a global reset sequence slave mode slave mode is to ensure having an ers-gr r-ers transition without a broken ers frame before grr. it requests to trigger/end the grr sequence through the pin which is similar to the grr bulb mode. the major difference to our existing sensor is to start the grr sequence after the end of the current frame instead of to start immediately in the next following row. figure 41: slave mode transition ers ers row reset integration readout r0x0100 mode_select[streaming] system state software standby streaming
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor gain ar0835hs_ds rev. d pub. 5/15 en 53 ?semiconductor components industries, llc, 2015. gain ar0835hs supports both analog and digital gain. analog gain analog gain is provided by colamp and adc reference scaling (there is no asc gain due to column parallel nature of architecture). only global (not per-color) coarse gain can be set by analog gain. global gain register (r0x305e) sets the analog gain. bits [1:0] set the colamp gain while bits [4:2] are reserved for adc gain. while the 2-bit colamp gain provides up to 4x analog gain, only lsb (bit [2]) of adc gain bits is utilized to support 2x adc gain. table 16 is the recommended gain setting: digital gain digital gain provides both per-color and fine (sub 1x) gain. the analog and digital gains are multiplicative to give the total gain. digita l gain is set by setting bits r0x305e[15:5] to set global gain or by indivi dually setting digital color gain r0x3056-c[15:5] where these 11 bits are designed in 4p7 format i.e. 4 msb provide gain up to 15x in step of 1x while 7 lsb provide sub-1x gain with a step size of 1/ 128. this sub-1x gain provides the fine gain control for the sensor. total gain max. total gain required by design spec is 8x (analog) and 16x (digital) with min. step size of 1/8. the total gain equation can be formulated as: (eq 17) where x is 6, 8, a, c, for gr, b, r and gb, respectively note: on semiconductor recommends using the registers mentioned above for gain set- tings. avoid r0x3028 to r0x3038 unless their mapping to above registers is well under- stood and taken into account. temperature sensor a standalone ptat based temperature sensor has been implemented. the block is controlled independent of se nsor timing and all communication happens through the two-wire serial interface. table 16: recommended analog gain setting colamp gain codes (r0x305e[1:0]) adc gain codes (r0x305e[4:2]) colamp gain adc gain total gain 0 0 000111 0 1 000212 1 0 000313 1 1 000414 1 0 001326 1 1 001428 total gain 1 dec r0x305e[1:0] ?? + ?? 1 r0x305e[2] + ?? ? dec r0x305x[15:5] ?? 128 ---------------- ----------------- ----------------- - ? =
ar0835hs_ds rev. d pub. 5/15 en 54 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor internal vcm driver internal vcm driver the ar0835hs utilizes an internal voice co il motor (vcm) driver. the vcm functions are register-control led through the serial interface. there are two output ports, vcm_isink and vcm_gnd, which would connect directly to the af actuator. take precautions in the design of the power supply routing to provide a low impedance path for the ground connection. appropriate filtering would also be required on the actuator supply. typical values would be a 0.1 ? f and 10 ? f in parallel. figure 42: vcm driver typical diagram table 17: vcm driver typical characteristic parameter minimum typical maximum units vcm_out voltage at vcm current sink 2.5 2.8 3.3 v wvcm voltage at vcm actuator 2.5 2.8 3.3 v inl relative accuracy C 1.5 4lsb res resolution C 8 C bits dnl differential nonlinearity C1 C +1 lsb ivcm output current 90 100 110 ma slew rate (user programmable) C C 13 ma/ms ar0835hs vcm_isink vcm_gnd vcm d gnd v vcm 10 f 0.1 f
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor spectral characteristics ar0835hs_ds rev. d pub. 5/15 en 55 ?semiconductor components industries, llc, 2015. spectral characteristics figure 43: quantum efficiency 0 10 20 30 40 50 60 70 400 500 600 700 800 red greenr greenb blue
ar0835hs_ds rev. d pub. 5/15 en 56 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor spectral characteristics figure 44: chief ray angle (cra) vs. image height cra vs. image height plot image height cra (%) (mm) (deg) 00 0 50.143 0.77 10 0.286 1.55 15 0.428 2.33 20 0.571 3.11 25 0.714 3.87 30 0.857 4.62 35 1.000 5.36 40 1.142 6.07 45 1.285 6.77 50 1.428 7.43 55 1.571 8.06 60 1.714 8.66 65 1.856 9.22 70 1.999 9.73 75 2.142 10.19 80 2.285 10.59 85 2.428 10.93 90 2.570 11.18 95 2.713 11.34 100 2.856 11.40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 102030405060708090100110 cra (deg) image height (%)
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics ar0835hs_ds rev. d pub. 5/15 en 57 ?semiconductor components industries, llc, 2015. electrical characteristics two-wire serial register interface the electrical characteristics of the two-wire serial register interface (s clk , s data ) are shown in figure 45 and table 18. table 19 on page 58 shows the timing specification for the two-wire serial interface. figure 45: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 18: two-wire serial register interface electrical characteristics f extclk = 25 mhz; v aa = 2.8v; v aa _pix = 2.8v; v dd _io = 1.8v; v dd _1v2 = 1.2v; v dd _pll = 1.2v; v dd _1v8 = 1.8v; output load = 68.5pf; t j = 55c symbol parameter condition min typ max unit v il input low voltage -0.5 C 0.3 x v dd _io v v ih input high voltage 0.7 x v dd _io C v dd _io + 0.5 v i in input leakage current no pull up resistor; v in = v dd _io or d gnd 10 C 14 ? a v ol output low voltage at specified 2ma 0.11 C 0.3 v i ol output low current at specified v ol 0.1v C C 6 ma c in input pad capacitance C C 6 pf c load load capacitance C C n/a pf sr s p s tsrts tstps tsds tsdh tsdv tsrth tf tr 9 th clock tbuf 1 st clock 9 th clock sdata sclk sdata sclk tlow thigh // // // // // // tacv 70% 30% 70% 30% 70% 30% 70% 30% 70% 70% 70% 30% 30% 30% 30% 30% 70% 70% 70% 70% 70% 30%
ar0835hs_ds rev. d pub. 5/15 en 58 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics extclk the electrical characteristics of the extclk input are shown in table 20. the extclk input supports an ac-coupled sine-wave input clock or a dc-coupled square-wave input clock. if extclk is ac-coupled to the ar0835hs and the clock is stopped, the extclk input to the ar0835hs must be driven to ground or to v dd _io. failure to do this will result in excessive current consumption within the extclk input receiver. table 19: two-wire serial interface timing specifications v dd _io = 1.7-1.9v; v aa = 2.4 -3.1v; environment temperature = -30c to 50c symbol definition min max unit f sclk s clk frequency 100 400 khz t high s clk high period 0.6 C ? s t low s clk low period 1.3 C ? s t srts start setup time 0.6 C ? s t srth start hold time 0.6 C ? s t sds data setup time 100 C ns t sdh data hold time 0 note ? s t sdv data valid time C 0.9 ? s t acv data valid acknowledge time C 0.9 ? s t stps stop setup time 0.6 C ? s t buf bus free time between stop and start 1.3 C ? s tr s clk and s data rise time C 300 ns tf s clk and s data fall time C 300 ns table 20: electrical characteristics (extclk) f extclk = 24 mhz; v aa = 2.8v; v aa _pix = 2.8v; v dd _io = 1.8v; v dd _1v2 = 1.2v; output load = 68.5pf; t j = 55c symbol parameter condition min typ max unit f extclk1 input clock frequency pll enabled 6 24 27 mhz t r input clock rise slew rate c load <20pf C 2.883 C ns t f input clock fall slew rate c load <20pf C 2.687 C ns v in _ ac input clock minimum voltage swing (ac coupled) C0.5C Cv (p-p) v in _ dc input clock maximum voltage swing (dc coupled) CCCv dd _io + 0.5 v f clkmax(ac) input clock signaling frequency (low amplitude) v in = v in _ ac (min) CC25mhz f clkmax(dc) input clock signaling frequency (full amplitude) v in = v dd _io C C 48 mhz clock duty cycle C 45 50 55 % t jitter input clock jitter cycle-to-cycle C 545 600 ps t lock pll vco lock time C C 0.2 2 ms c in input pad capacitance C C 6 C pf i ih input high leakage current C 0 C 10 ? a
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics ar0835hs_ds rev. d pub. 5/15 en 59 ?semiconductor components industries, llc, 2015. figure 46: fall slew rates (cap load = 25pf) v ih input high voltage 0.7 x v dd _io C v dd _io + 0.5 v v il input low voltage -0.5 C 0.3 x v dd _io v table 20: electrical characteristics (extclk) f extclk = 24 mhz; v aa = 2.8v; v aa _pix = 2.8v; v dd _io = 1.8v; v dd _1v2 = 1.2v; output load = 68.5pf; t j = 55c symbol parameter condition min typ max unit v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io
ar0835hs_ds rev. d pub. 5/15 en 60 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics figure 47: rise slew rates (cap load = 25pf) high speed serial pixel data interface the high speed serial pixel (hispi) interface uses four data and one clock low voltage differential signaling (lvds) outputs. ?slvsc_p ?slvsc_n ?slvs0_p ?slvs0_n ?slvs1_p ?slvs1_n ?slvs2_p ?slvs2_n ?slvs3_p ?slvs3_n v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io v dd _io
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics ar0835hs_ds rev. d pub. 5/15 en 61 ?semiconductor components industries, llc, 2015. the hispi interface supports three protocols, streaming s, streaming sp, and packetized sp. the streaming protocols conform to a stan dard video application where each line of active or intra-frame bl anking provided by the sensor is transmitted at the same length. the packetized sp protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. these protocols are further described in the high-speed serial pixel (hispi) interface protocol specification v1.50.00. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) clock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. a collection of one clock lane plus four data lanes is called a phy.figure 48 shows the configuration between the hispi transmitter and the receiver. figure 48: hispi transmitter and receiver interface block diagra m (hispi mode only) hispi physical layer the ar0835hs phy will serialize an 8-or 10-bit data word and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of clock. figure 49 shows bit transmission. in this example, the wo rd is transmitted in order of msb to lsb. the receiver latches data at the ri sing and falling edge of the clock. a camera containing the hispi transmitter a host (dsp) containing the hispi receiver dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0 tx phy0 rx phy0 dp0 dn0 dp1 dn1 dp2 dn2 dp3 dn3 cp0 cn0
ar0835hs_ds rev. d pub. 5/15 en 62 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics figure 49: timing diagram dll timing adjustment the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the rece iver circuits and can be used to compensate for skew introduced in pcb design. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation. figure 50: block diagram of dll timing adjustment c p dn . . msb lsb txpost dp cn 1 ui txpre delay del0[2:0] delay del1[2:0] delay delay del3[2:0] delay del2[2:0] data_lane 0 data_lane 1 clock _lane 0 data_lane 2 data_lane 3 delclock[2:0]
ar0835hs_ds rev. d pub. 5/15 en 63 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics figure 51: delaying the clock_lane with respect to data_lane figure 52: delaying data_lane with respect to the clock_lane hispi streaming mode protocol layer the hispi protocol is described hispi protocol v1.50.00. datan (de ln = 000) cp ( delclock = 000) cp ( delclock = 001) cp (delclock = 010) cp (de lclock = 011) cp ( delclock = 100) cp (d elcloc k = 1 01) c p (delclock = 110) cp ( delclock =111) increasing delclock_[2:0] increases clock delay 1 ui 1 ui t dllstep cp ( delclock = 000) datan (deln = 000) datan(deln = 001) datandeln = 010) datan(deln = 011) datan(deln = 100) datan(deln = 101) datan(deln = 110) datan(deln = 111) increasing deln_[2:0] increases data delay
ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics ar0835hs_ds rev. d pub. 5/15 en 64 ?semiconductor components industries, llc, 2015. serial pixel data in terface (hispi mode) the electrical characteristics of the seri al pixel data interface (clk_p, clk_n, data[4:1]_p, and data[4:1]_n) are shown in table 21 and table 22 notes: 1. one ui is defined as the normalized mean ti me between one edge and the following edge of the clock. 2. taken from the 0v crossing point with the dll off. 3. also defined with a maximum loading capacitance of 10 pf on any pin. the loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 ui. 4. the total skew between the clock lane and any da ta lane in the same phy between any edges; it includes clock duty cycle, mean skew and total peak jitter at ber of 1e-9. 5. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edge s at mean vcm point. note that differential skew also is related to the ? vcm_ac spec which also must not be exceeded. table 21: slvs electrical timing specification parameter symbol min max unit notes data rate 1/ui 280 1000 mbps 1 bitrate period t pw 1.00 3.57 ns 1 max setup time from transmitter t pre 0.3 ui 1, 2 max hold time from transmitter t post 0.3 ui 1, 2 eye width t eye 0.6 ui 1, 2 data total jitter (pk-pk) @1e-9 t totaljit 0.2 ui 1, 2 clock period jitter (rms) t ckjit 50 ps 2 clock cycle-to-cycle jitter (rms) t cycjit 100 ps 2 rise time (20% - 80%) t r 150ps 0.25 ui 3 fall time (20% - 80%) t f 150ps 0.25 ui 3 clock duty cycle d cyc 45 55 % 2 total clock to data skew t chskew -0.2 0.2 ui 1, 4 mean differential skew t diffskew -100 100 ps 5 table 22: slvs electrical dc specification tj = 25c parameter symbol min typ max unit slvs dc mean common mode voltage vcm 0.45*v dd _tx 0.5*v dd _tx 0.55*v dd _tx v slvs dc mean differential output voltage |vod| 0.36*v dd _t 0.5*v dd _tx 0.64*v dd _tx v change in vcm between logic 1 and 0 ? vcm 25 mv change in |vod| between logic 1 and 0 | vod| 25 mv vod noise margin nm 30 % difference in vcm between any two channels | ? vcm| 30 mv difference in vod between any two channels | ? vod| 50 mv common-mode ac voltage (pk) without vcm cap termination vcm_ac 50 mv common-mode ac voltage (pk) with vcm cap termination vcm_ac 30 mv maximum overshoot peak |vod| vod_ac 1.3*|vod| v maximum overshoot vdiff pk-pk vdiff_pkpk 2.6*vod v
ar0835hs_ds rev. d pub. 5/15 en 65 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics control interface the electrical characteristics of the cont rol interface (reset_bar, test, gpio0, gpio1, gpi2, and gpi3) are shown in table 23. operating voltages v aa and v aa _pix must be at the same potential for correct operation of the ar0835hs. single-ended output impedance ro 35 50 70 output impedance mismatch ? ro 20 % table 23: dc electrical charac teristics (control interface) f extclk = 24 mhz; v aa = 2.8v; v aa _pix = 2.8v; v dd _io = 1.8v; dv dd _1v2 = 1.2v; output load = 68.5pf; t j = 55c symbol parameter condition min typ max unit v ih input high voltage 0.7 x v dd _io C v dd _io + 0.5 v v il input low voltage C0.5 C v dd _io x 0.3 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd CC10 ? a c in input pad capacitance C 6 C pf table 24: dc electrical defi nitions and characteristics f extclk = 24 mhz; v aa = 2.8v; v aa _pix = 2.8v; v dd _io = 1.8v; v dd _1v2 = 1.2v; output load = 68.5pf; t j = 70c; mode = full resolution (3264x2488); frame rate = 30 fps symbol parameter condition min typ max unit v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _1v2 digital voltage 1.14 1.2 1.3 v v dd _1v8 phy digital voltage 1.7 1.8 1.9 v v dd _io i/o digital voltage 1.7 1.8 1.9 v 2.5 2.8 3.1 v v dd slvs_phy hispi analog supply internal regulator disabled 0.35 0.4 0.45 v internal regulator enabled 1.14 1.2 1.3 v dd _phy hispi digital supply 1.14 1.2 1.3 v h/w standby current consumption CC30 ? a output driving strength 10 C C ma slew rate C0.7-C ? v/sec programming voltage for otpm (v pp ) 66.57 v table 22: slvs electrical dc specification tj = 25c parameter symbol min typ max unit
ar0835hs_ds rev. d pub. 5/15 en 66 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor electrical characteristics typical operating current consumption absolute minimum an d maximum ratings caution stresses greater than those listed in table 26 may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect reliabil- ity. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operat ional sections of this specification is not implied. table 25: typical operating current consumption nominal voltages: f extclk = 24mhz; v aa = 2.8v; v aa _pix = 2.8v; v dd _1v8 = 1.8v; v dd _io = 1.8v; v dd _1v2 = 1.2v tj = 25c symbol parameter min typ max unit i(v aa ) analog supply current 8mp, 46fps -- 85 110 ma 6mp, 60fps -- 85 110 ma 1080p, 60fps -- 85 110 ma 720p, 120fps -- 85 110 ma i(v aa _pix) pixel supply current 8mp, 46fps -- 16 20 ma 6mp, 60fps -- 16 20 ma 1080p, 60fps -- 16 20 ma 720p, 120fps -- 16 20 ma i(v dd _1v8) otpm read supply current 8mp, 46fps -- 0 1 ma 6mp, 60fps -- 0 1 ma 1080p, 60fps -- 0 1 ma 720p, 120fps -- 0 1 ma i(v dd _io) i/o supply current 8mp, 46fps -- 1 2 ma 6mp, 60fps -- 1 2 ma 1080p, 60fps -- 1 2 ma 720p, 120fps -- 1 2 ma i(v dd _1v2: v dd sw, v dd _ana, v dd _pll) core supply current 8mp, 46fps -- 150 175 ma 6mp, 60fps -- 150 175 ma 1080p, 60fps -- 130 165 ma 720p, 120fps -- 130 140 ma i(v dd _phy, v dd slvs_phy) phy supply current 8mp, 46fps -- 12 14 ma 6mp, 60fps -- 12 14 ma 1080p, 60fps -- 10 12 ma 720p, 120fps -- 8 10 ma table 26: absolute max voltages symbol parameter min max unit 1.2v all1.2v supply -0.3 1.5 v 1.8v all1.8v supply -0.3 2.1 v 2.8v all 2.8v supply -0.3 3.5 v
ar0835hs_ds rev. d pub. 5/15 en 67 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor hispi specification reference hispi specification reference the sensor design and this documentation is based on the following hispi specifica- tions: ? hispi protocol specification v1.50.00 ? hispi physical layer specification v3.0 mipi specification reference the sensor design and this documentation is based on the following mipi specifica- tions: ? mipi alliance standard for csi-2 version 1.0 ? mipi alliance standard for d-phy version 1.0
ar0835hs_ds rev. d pub. 5/15 en 68 ?semiconductor components industries, llc, 2015 ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor package diagram package diagram figure 53: clcc package diagram
ar0835hs_ds rev. d pub. 5/15 en 69 ?semiconductor components industries, llc, 2015. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor package diagram figure 54: clcc package pinout diagram 35 v dd _slvs 36 data_n 37 data_p 38 d gnd 39 v dd _sw 40 test 41 v dd _io 42 extclk 34 data2_n 33 data2_p 32 v dd _phy 31 clk_p data3_n 28 data3_p 29 data4_n 26 data4_p 25 d gnd _ana 19 v dd _ana 20 1 v dd _sw v dd _sw 24 v dd _1v8 27 v dd _1v8 23 v pp 22 v dd _ana 21 clk_n 30 5 v dd _sw 47 v dd _pll 43 d gnd 46 d gnd 48 d gnd 2 d gnd 45 s data 44 s clk 3 gpi2 4 gpi3 6 gpio0 a gnd 14 a gnd 17 d gnd _ana 18 atest1 13 v aa 15 v aa 16 v aa _pix 12 pixgnd 11 vcm_isink 10 vcm_gnd 9 xshutdown 8 gpio1 7
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. ar0835hs: 1/3.2-inch 8 mp cmos digital image sensor revision history ar0835hs_ds rev. d pub. 5/15 en 70 ?semiconductor components industries, llc, 2015 . a-pix is a trademark of semiconductor components industries, llc (s cillc) or its subsidiaries in the united states and/or other countries. revision history rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/13/15 ? converted to on semiconductor template ? removed confidential marking ? updated ?ordering information? on page 2 rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/9/14 ? updated to production ? updated ?features? on page 1 ? updated table 1, ?available part numbers,? on page 1 ? updated table 1, ?key performance parameters,? on page 1 ? updated table 2, ?modes of operatio n and power consumption,? on page 2 ? updated ?general description? on page 6 ? updated ?functional overview? on page 6 ? updated figure 6: ?recommended power-down sequence,? on page 14 ? updated ?functional overview? on page 6 ? updated table 25, ?typical operating current consumption,? on page 66 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/16/13 ? changed the part no. on page 1. ? updated ?features? on page 1 ? updated table 1, ?key performance parameters,? on page 1 ? updated table 2, ?modes of operatio n and power consumption,? on page 2 ? updated ?general description? on page 6 ? updated figure 15: ?clocking configuration (pll),? on page 26 ? updated figure 53: ?clcc package diagram,? on page 68 ? updated table 27, ?pin connection table,? on page 72 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/1/12 ? initial release?programming and verifying the otpm? on page 31

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